1 data sheet acquired from harris semiconductor schs055 features ? high-voltage types (20v rating) ? cd4070b - quad exclusive-or gate ? cd4077b - quad exclusive-nor gate ? medium speed operation -t phl , t plh = 65ns (typ) at v dd = 10v, c l = 50pf ? 100% tested for quiescent current at 20v ? standardized symmetrical output characteristics ? 5v, 10v and 15v parametric ratings ? maximum input current of 1 m a at 18v over full package temperature range - 100na at 18v and 25 o c ? noise margin (over full package temperature range) - 1v at v dd = 5v, 2v at v dd = 10v, 2.5v at v dd = 15v ? meets all requirements of jedec standard no. 13b, standard speci?cations for description of b series cmos devices applications ? logical comparators ? adders/subtractors ? parity generators and checkers description the harris cd4070b contains four independent exclusive- or gates. the harris cd4077b contains four independent exclusive-nor gates. the cd4070b and cd4077b provide the system designer with a means for direct implementation of the exclusive-or and exclusive-nor functions, respectively. pinouts ordering information part number temp. range ( o c) package pkg. no. CD4070BE -55 to 125 14 ld pdip e14.3 cd4077be -55 to 125 14 ld pdip e14.3 cd4070bf -55 to 125 14 ld cerdip f14.3 cd4077bf -55 to 125 14 ld cerdip f14.3 cd4070bm -55 to 125 14 ld soic m14.15 cd4077bm -55 to 125 14 ld soic m14.15 cd4070b (pdip, cerdip, soic) top view cd4077b (pdip, cerdip, soic) top view a b j = a ? b k = c ? d c d v ss v dd h g m = g ? h l = e ? f f e 1 2 3 4 5 6 7 14 13 12 11 10 9 8 a b j = a ? b k = c ? d c d v ss v dd h g m = g ? h l = e ? f f e 1 2 3 4 5 6 7 14 13 12 11 10 9 8 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1998 cd4070b, cd4077b cmos quad exclusive-or and exclusive-nor gate file number 910.1 [ /title (cd40 70b, cd407 7b) / sub- j ect (cmo s quad exclu- sive- or and exclu- sive- nor gate) / autho r () / key- words (har- ris semi- con- ductor, cd400 0, metal gate, cmos , pdip, cerdip, mil, january 1998
2 functional diagrams cd4070b cd4077b a b c d e f g h 1 2 5 6 8 9 12 13 3 4 10 11 j = a ? b k = c ? d m = g ? h l = e ? f v ss = 7 v dd = 14 j k l m a b c d e f g h 1 2 5 6 8 9 12 13 3 4 10 11 j=a ? b k = c ? d m = g ? h l=e ? f j k l m figure 1. schematic diagram for cd4070b (1 of 4 identical gates) cd4070b truth table (1 of 4 gates) abj 000 101 011 110 note: 1 = high level 0 = low level j = a ? b v dd v ss v ss v dd v dd v ss v ss v dd p n p n p n p p n p n j 3(4,10,11) b ? 2(5,9,12) a ? 1(6,8,13) ? inputs protected by cmos protection network figure 2. schematic diagram for cd4077b (1 of 4 identical gates) cd4077b truth table (1 of 4 gates) abj 001 100 010 111 note: 1 = high level 0 = low level j = a ? b v dd v ss v ss v dd v dd v ss v ss v dd p n p n p n p n p n j 3(4,10,11) b ? 2(5,9,12) a ? 1(6,8,13) ? inputs protected by cmos protection network n cd4070b, cd4077b
3 absolute maximum ratings thermal information dc supply voltage range (v dd ) . . . . . . . . . . . . . . . . . -0.5v to 20v input voltage range, all inputs . . . . . . . . . . . . . . -0.5v to v dd 0.5v dc input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range (typical) . . . . . . . . . . . . . . . . . . . . 3v to 18v thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 90 n/a cerdip package . . . . . . . . . . . . . . . . 95 38 soic package . . . . . . . . . . . . . . . . . . . 175 n/a maximum junction temperature (hermetic package or die )175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter conditions limits at indicated temperatures ( o c) units -55 -40 85 125 25 v o (v) v in (v) v dd (v) min typ max quiescent device current i dd max - 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 m a - 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 m a - 0, 15 15 1 1 30 30 - 0.01 1 m a - 0, 20 20 5 5 150 150 - 0.02 5 m a output low (sink) current i ol min 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - ma 0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - ma 1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - ma output high (source) current i oh min 4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - ma 2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - ma 9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - ma 13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - ma output voltage: low level, v ol max - 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 v - 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 v - 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 v output voltage: high level, v oh min - 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - v - 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - v - 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - v input low voltage, v il max 0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 v 1, 9-103333--3v 1.5, 13.5 - 15 4444--4v input high voltage, v ih min 0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - v 1, 9-1077777--v 1.5, 13.5 - 15 11 11 11 11 11 - - v input current, i in max - 0, 18 18 0.1 0.1 1 1- 10 -5 0.1 m a cd4070b, cd4077b
4 ac electrical speci?cations t a = 25 o c, input t r , t f = 20ns, c l = 50pf, r l = 200k w parameter symbol test conditions limits on all types units v dd (v) typ max propagation delay time t phl , t plh 5 140 280 ns 10 65 130 ns 15 50 100 ns transition time t thl , t tlh 5 100 200 ns 10 50 100 ns 15 40 80 ns input capacitance c in any input 5 7.5 pf typical performance curves figure 3. typical output low (sink) current characteristics figure 4. minimum output low (sink) current characteristics figure 5. typical output high (source) current characteristics figure 6. minimum output high (source) current characteristics t a = 25 o c gate to source voltage (v gs ) = 15v 10v 5v 30 25 20 15 10 5 0 0 5 10 15 i ol , output low (sink) current (ma) v ds , drain to source voltage (v) t a = 25 o c gate to source voltage (v gs ) = 15v 10v 5v 15 12.5 10 7.5 5 2.5 0 0 5 10 15 i ol , output low (sink) current (ma) v ds , drain to source voltage (v) t a = 25 o c gate to source voltage (v gs ) = -5v -10v -15v -5 -10 -15 -20 -25 -30 0 0 -5 -10 -15 i oh , output high (source) current (ma) v ds , drain to source voltage (v) t a = 25 o c gate to source voltage (v gs ) = -5v -10v -15v -15 -10 -5 0 0 -5 -10 -15 i oh , output high (sink) current (ma) v ds , drain to source voltage (v) cd4070b, cd4077b
5 figure 7. typical transition time as a function of load capacitance figure 8. typical propagation delay time as a function of load capacitance figure 9. typical propagation delay time as a function of supply voltage figure 10. typical dynamic power dissipation as a function of input frequency typical performance curves (continued) t a = 25 o c supply voltage (v dd ) = 5v 10v 15v 200 150 100 50 0 0204060 t thl , t tlh , transition time (ns) c l , load capacitance (pf) 80 100 110 t a = 25 o c supply voltage (v dd ) = 5v 10v 15v 300 200 100 0 0204060 t phl , t plh , propagation delay time (ns) c l , load capacitance (pf) 80 100 t a = 25 o c 300 200 100 0 0 5 10 15 t phl , t plh , propagation delay time (ns) v dd , supply voltage (v) 20 load capacitance c l = 50pf t a = 25 o c supply voltage (v dd ) = 15v 5v 10 3 10 2 10 1 10 -1 10 -1 110 10 2 p d , power dissipation ( m w) f i , input frequency (khz) 10 3 10 4 10 4 10 5 10v c l = 50pf c l = 15pf 10v cd4070b, cd4077b
6 cd4070b, cd4077b dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b 0.010 (0.25) c a m b s e d d1 a a2 l a1 -a- notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpen- dicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e14.3 (jedec ms-001-aa issue d) 14 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n14 149 rev. 0 12/93
7 cd4070b, cd4077b ceramic dual-in-line frit seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- a d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa c a - b m d s s e a f14.3 mil-std-1835 gdip1-t14 (d-1, configuration a) 14 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.785 - 19.94 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 a 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n14 148 rev. 0 4/94
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
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